Test Challenges of Nanometer Technology
نویسنده
چکیده
DFT. The last 30 years have demonstrated that short time-to-market, low cost, and high product quality can only be achieved if test is part of the design and optimized for manufacturing. Structural DFT methodologies based on scan with voltage-based test, supplemented by Iddq test, provided predictable test quality and a basis for automation of test synthesis and test pattern generation. Scan also provided effective means for silicon debug and diagnostics. Memory BIST has been widely adopted for testing embedded memories.
منابع مشابه
A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies
This paper addresses the critical issue of scaling limits of local interconnects, contact plugs and local vias made of metal. It is shown that the current carrying capacity of copper vias/contacts fails to meet ITRS current density requirements beyond the 45 nm technology node. Additionally, the electrical properties of local interconnects/vias made of carbon nanotube (CNT) arrays are analyzed ...
متن کاملTough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction
Rohit Kapur Thomas W. Williams Synopsys Inc. P lay the word association game with electronics, and the first words that come to mind might be “inexpensive” and “reliable.” Everyone expects electronic items to become continually less expensive and quickly outdated. We also expect them to work when we bring them home. Do any of us ever question how and why this happens? A large part of the answer...
متن کاملChallenges and Opportunities for Design Innovations in Nanometer Technologies
The driving force behind the spectacular advancement of the integrated circuit technology in the past thirty years has been the exponential scaling of the feature size, i.e., the minimum dimension of a transistor. It has been following the Moore’s Law [1] at the rate of a factor of 0.7 reduction every three years. It is expected that such exponential scaling will continue for at least another 1...
متن کاملCMOS Scaling into the Nanometer Regime
Starting with a brief review on 0.1m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number f...
متن کاملInnovative Test Techniques for Advanced Technology Nodes
The introduction of nanometer technologies, has allowed the semiconductor industry to keep pace with increased performance-capacity demands from consumers. This has brightened the prospects for future industry growth; however, new technologies come with new challenges. Semiconductor test costs have been growing steadily. Testing techniques for integrated circuits are today facing many exciting ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2003